1. Field of the Invention
The present invention relates to bus communication systems that use an intermediate bus in a computer system that has an expansion bridge and a host bridge connected to the intermediate bus.
2. Description of Related Art
In most computer systems, a central processing unit ("CPU") is the center of processing activity. In order to communicate with peripheral devices, such as printers, the CPU utilizes a communication system that typically includes a bus to which a plurality of devices are connected. This bus may be termed the "intermediate" bus. In one configuration, the CPU is connected to a host bridge, which manages communication between the CPU and the intermediate bus.
In addition to single devices coupled to the intermediate bus, additional buses can be coupled to the intermediate bus. In order to accomplish this, one or more expansion bridges are coupled to the intermediate bus which manage communication between the intermediate bus and the expansion bus. Any of a number of different peripherals and types of peripherals can be connected to the expansion bus. For example, slave peripherals, DMA slaves, and bus masters could be coupled to the expansion bus to communicate through the expansion bridge to the host bridge and the CPU and other circuitry, such as Random Access Memory that may be coupled to the host bridge.
Industry-wide standards have been set up to standardize the interface between the expansion bridge and the host bridge. One industry standard is that an expansion bus cannot be preempted once access is granted, according to industry standard expansion bus rules such as the Industry Standard Architecture ("ISA") rules. In other words, an expansion bridge must always be allowed to complete its cycle subsequent to its access. A second industry standard is that, for coherency reasons, read cycles originating from the expansion bridge cannot pass data posted in the CPU buffer, which is positioned between the CPU and the intermediate bus. In other words, any read cycles from the intermediate bus cannot pass data posted within the host bridge and therefore cannot accept the cycle until the CPU buffer in the host bridge is empty.
During operation, it is possible that some systems adhering to these constraints can lock up and become nonfunctional. A deadlock can occur if a CPU cycle that targets the expansion bus is posted in the CPU buffer at the same time that an expansion bridge cycle has started up. For example, if the CPU cycle that targets the expansion bridge posts to the CPU buffer, and an expansion bus master is granted bus access, the expansion master's attempt to read DRAM will not be successful (i.e., will not be allowed to complete) because the CPU buffer is not empty. At the same time, the expansion bridge will not give up control of the bus to receive the information posted in the CPU buffer until its operations have completed. Because the expansion bridge cannot complete and will not give up, the result is deadlock.
Prior chip sets that support bus concurrency between a CPU and intermediate bus require special sideband signals to prevent deadlock and provide a guaranteed response time to expansion bridge traffic, particularly that targeting DRAM. The term "Guaranteed Access Timing" ("GAT") is used to describe systems having this guaranteed response time and a deadlock prevention mechanism. Systems implementing GAT have previously implemented a special sideband coupling that provides three additional buffer management sideband signals in order to provide GAT operation.
In order to address the deadlock problem in previous systems, expansion bridges have used the special sideband coupling to assert a flush request signal ("FLSHREQ") that commands the host bridge to empty the CPU buffer and to disable further posting while it remains asserted. This special sideband coupling increases hardware cost, and it would be an advantage to eliminate it while still maintaining its functionality.
Another problem relates to the access completion latency of any transaction over the expansion bridge. Industry-wide standards, although varying in the exact amount of time, generally require a maximum time during which the bus cycle can be stalled or held in wait states awaiting data availability. This time may be referred to as an access completion latency time. For example, according to ISA "AT" compatibility standards, the maximum access completion latency time via the "IOCHRDY" signal must be less than 2.5 .mu.s.
Achieving this specification can be difficult in some circumstances. For example, this specification may be violated if the cycle targets DRAM and the DRAM buffer has data stored in it when the bus request is granted. Due to the additional time necessary to flush the DRAM buffer, a latency violation could occur.
In order to ensure that the access completion latency period is within the maximum requirement, previous systems have used the special purpose sideband coupling to assert a memory request ("MEMREQ") signal to empty the DRAM buffer, and maintain it in its flushed condition by disabling further posting while it remains asserted. To properly use this signal, the expansion bridge is required to assert the MEMREQ signal to empty the DRAM buffer before starting any communication cycle. The special sideband coupling increases hardware cost, and it would be advantageous to eliminate it.
Another problem (the "bus acquisition" problem) created by the expansion bridge is the possibility of bus back-up. Once the expansion bridge has granted access to a non-preemptible bus agent, the bus grant is locked until the expansion bridge decides to release the bus. In other words, the arbiter cannot take the bus away. The problem is that some expansion bridge devices have very low bandwidth and can hold the intermediate bus for lengthy periods of time. During these periods, all other agents on the intermediate bus are prevented from using it. As a result, these other agents may have a very long bus acquisition latency before they are granted the bus.
In addition to providing a guaranteed access latency, it would be an advantage to provide a system that guarantees bounded, quantifiable intermediate bus acquisition latency in systems with expansion bus bridges.